It is known to provide memory controllers which serve the function of generating appropriate signals to perform data accesses (both reads and writes) to memory taking into account the requirements for control signals, setup, timing and other matters required by the memory concerned.
Typical design requirements for memory controllers are the ability to cope with different memory types, the ability to drive periodic refresh, the ability to deal with clock domain crossing and, bus width conversion and to exploit the provision of open pages and access reordering which are possible with some memory configurations in order to increase throughput and/or meet quality-of-service requirements.
It is also known within integrated circuit design to produce so called system-on-chip integrated circuits in which different functional blocks are joined together by interconnect structures, such as the AXI compliant interconnects produced by ARM Limited of Cambridge, England. One problem which can arise in this context are data hazards such as read-after-write hazards which can be introduced by the reordering of data accesses permitted by interconnect structures. Reordering is desirable in order to improve throughput, but gives rise to complication in avoiding hazards. One way to avoid hazards is to delay returning a write response for a write access until after the data has actually been written to memory such that a subsequent read access will not be attempted until after the write has actually been made. However, this approach has the result that the write accesses incur the full memory latency penalty. If a write response is returned before the write is made (i.e. with the write being buffered), then it is necessary to have some hazard detection logic that records such dependencies and ensures that a read access to the same address as a pending write does get the correct data. U.S. Pat. No. 7,213,095 describes one example of such hazard detection logic. Dependent accesses (commands) with such a system are held until the commands upon which they are dependent have completed.
The interface between a memory controller and a memory can often represent a significant bottleneck in the performance of a data processing system. It is common for memories to be provided off-chip and this can result in an increase in the energy required to make memory accesses and the latency associated with such memory accesses.
It is also known to provide write buffers which are able to merge write requests into longer requests which can be made more efficiently to an attached memory device.
U.S. Pat. No. 7,020,751 describes various techniques for write back control of a cache memory that seek to improve speed and/or efficiency.